This invention generally relates to stacked capacitors for integrated circuit chips. More particularly, it relates to a DRAM cell structure and a method for fabrication thereof in which a stacked capacitor is self-aligned to the underlying bitline.
Stacked capacitors have been extensively used for charge storage in high density DRAM cells. One type of stacked capacitor is a stud stacked capacitor in which a polysilicon stud is defined, coated with dielectric, and then the dielectric is coated with a conformal layer of polysilicon. Other stacked capacitors have multiple planar layers or vertical cylinders of polysilicon separated by oxide. While stacked capacitors provide advantages for DRAM cells they suffer from several problems. First, there is the problem of overlay mismatch between capacitor plate and node diffusion which can lead to high contact resistance. Second, stacked capacitors have very uneven topography in the array region, making subsequent processing steps, such as photolithography difficult. Third, contact between bitline and bitline diffusion through thick oxide encapsulating the stacked capacitor is difficult. Fourth, photolithographic misalignment of the stacked capacitor to underlying structures contributes to chip to chip variation of the size and capacitance of the stacked capacitor. Fifth, the vertical dimension of the stacked capacitor is limited by the ability to tolerate the topology it contributes and the planar area of the stacked capacitor is limited by the dimensions of the cell. Finally, stacked capacitors pose the need for additional masks to provide the node and bitline contacts.
Thus, a better solution is needed that provides improved overlay between capacitor plate and node diffusion, improved overlay between capacitor plate and bitline, simplified contact to bitline and node diffusions, the ability to extend more vertically while retaining smooth topology, less variation in capacitance among cells, better use of cell area, and all without additional masks. This solution is provided by the following invention.
It is therefore an object of the present invention to provide a DRAM cell stacked capacitor self-aligned to a bitline
It is another object of the present invention to provide a DRAM chip having uniform topology in array and supports circuits portions of the chip to facilitate processing of subsequent wiring levels.
It is another object of the present invention to provide a stacked capacitor occupying nearly all of the area of a cell.
It is a feature of the present invention that portions of a single level of metallization are patterned in separate masking steps.
It is an advantage of the present invention that the stacked capacitor can occupy substantially all the area of a cell except that taken by isolation having a dimension substantially less than the minimum dimension of the photolithographic system used in the fabrication process.
These and other objects, features, and advantages of the invention are accomplished by a method of forming a connector, comprising the steps of: depositing a conductive layer; patterning at least portions of the conductive layer; forming an insulating layer on the conductive layer; and patterning at least portions of the insulating layer and the conductive layer.
Another aspect of the invention is a DRAM cell structure, comprising a stacked capacitor self-aligned to a bitline.